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NTP18N06L, NTB18N06L Power MOSFET 15 Amps, 60 Volts, Logic Level
N-Channel TO-220 and D2PAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Typical Applications http://onsemi.com
* * * *
Power Supplies Converters Power Motor Controls Bridge Circuits
15 AMPERES 60 VOLTS RDS(on) = 100 mW
N-Channel D
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 mW) Gate-to-Source Voltage - Continuous - Non-Repetitive (tp v 10 ms) Drain Current - Continuous @ TC = 25C - Continuous @ TC = 100C - Single Pulse (tp v 10 ms) Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, VDS = 60 Vdc, IL(pk) = 11 A, L = 1.0 mH, RG = 25 W) Thermal Resistance - Junction-to-Case - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS Value 60 60 "10 "20 15 8.0 45 48.4 0.32 -55 to +175 61 Adc Adc Apk Watts W/C C mJ Unit Vdc Vdc Vdc 4 4 1 TO-220AB CASE 221A STYLE 5 2 3 2 3 D2PAK CASE 418AA STYLE 2 S G
ID ID IDM PD TJ, Tstg EAS
1
MARKING DIAGRAMS & PIN ASSIGNMENTS
4 Drain 4 Drain
C/W RqJC RqJA TL 3.1 72.5 260 C
NTx18N06L LLYWW NTx18N06L LLYWW 1 Gate 1 3 Gate Source NTx18N06L 2 x Drain LL Y WW 2 Drain 3 Source
= Device Code = B or P = Location Code = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2003
1
October, 2003 - Rev. 3
Publication Order Number: NTP18N06L/D
NTP18N06L, NTB18N06L
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 1) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 60 Vdc) (VGS = 0 Vdc, VDS = 60 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (Note 1) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 1) (VGS = 5.0 Vdc, ID = 7.5 Adc) Static Drain-to-Source On-Voltage (Note 1) (VGS = 5.0 Vdc, ID = 15 Adc) (VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150C) Forward Transconductance (Note 1) (VDS = 7.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 15 Adc, Vd Ad VGS = 5.0 Vdc) (Note 1) SOURCE-DRAIN DIODE CHARACTERISTICS Diode Forward On-Voltage Reverse Recovery Time (IS = 15 Adc, VGS = 0 Vdc, Adc Vdc dIS/dt = 100 A/ms) (Note 1) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 2. Switching characteristics are independent of operating junction temperature. (IS = 15 Adc, VGS = 0 Vdc) (Note 1) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR - - - - - - 0.96 0.83 35 23 12 0.043 1.2 - - - - - mC Vdc ns (VDD = 30 Vdc, ID = 15 Adc, VGS = 5.0 Vdc, 5 0 Vdc RG = 9.1 W) (Note 1) td(on) tr td(off) tf Qt Q1 Q2 - - - - - - - 11 121 11 42 7.3 1.9 4.3 20 210 40 80 20 - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss - - - 310 106 37 440 150 70 pF VGS(th) 1.0 - RDS(on) - VDS(on) - - gFS - 1.46 1.2 9.4 1.8 - - mhos 85 100 Vdc 1.6 4.2 2.0 - Vdc mV/C mW V(BR)DSS 60 - IDSS - - IGSS - - - - 1.0 10 100 nAdc 70 63.2 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
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NTP18N06L, NTB18N06L
32 VGS = 10 V ID, DRAIN CURRENT (AMPS) 24 8V 6V 5V 4.5 V 16 4V 8 3.5 V 3V 0 0 2 4 6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 8 ID, DRAIN CURRENT (AMPS) 32 VDS 10 V
24
16
8
TJ = 25C TJ = 100C TJ = -55C 7
0
1
2 3 4 5 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.32 VGS = 5 V 0.24 TJ = 100C 0.16 TJ = 25C 0.08 TJ = -55C
0.32 VGS = 10 V 0.24
0.16
TJ = 100C
TJ = 25C 0.08 TJ = -55C 0 0 8 16 24 ID, DRAIN CURRENT (AMPS) 32
0 0 24 8 16 ID, DRAIN CURRENT (AMPS) 32
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 3. On-Resistance versus Gate-to-Source Voltage
Figure 4. On-Resistance versus Drain Current and Gate Voltage
2 1.8 1.6 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) 175 ID = 7.5 A VGS = 5 V
10,000
VGS = 0 V TJ = 150C
IDSS, LEAKAGE (nA)
1000
100 TJ = 100C 10
1
0
10 20 30 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
60
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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NTP18N06L, NTB18N06L
POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge a voltage corresponding to the off-state condition when controlled. The lengths of various switching intervals (Dt) calculating td(on) and is read at a voltage corresponding to the are determined by how fast the FET input capacitance can on-state when calculating td(off). be charged by current from the generator. At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET The published capacitance data is difficult to use for source lead, inside the package and in the circuit wiring calculating rise and fall because drain-gate capacitance which is common to both the drain and gate current paths, varies greatly with applied voltage. Accordingly, gate produces a voltage at the source which reduces the gate drive charge data is used. In most cases, a satisfactory estimate of current. The voltage is determined by Ldi/dt, but since di/dt average input current (IG(AV)) can be made from a is a function of drain current, the mathematical solution is rudimentary analysis of the drive circuit so that complex. The MOSFET output capacitance also t = Q/IG(AV) complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the During the rise and fall time interval when switching a resistance of the driving source, but the internal resistance resistive load, VGS remains virtually constant at a level is difficult to measure and, consequently, is not specified. known as the plateau voltage, VSGP. Therefore, rise and fall The resistive switching time variation versus gate times may be approximated by the following: resistance (Figure 9) shows how typical switching tr = Q2 x RG/(VGG - VGSP) performance is affected by the parasitic circuit elements. If tf = Q2 x RG/VGSP the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. where The circuit used to obtain the data is constructed to minimize VGG = the gate drive voltage, which varies from zero to VGG common inductance in the drain and gate circuit loops and RG = the gate drive resistance is believed readily achievable with board mounted and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which During the turn-on and turn-off delay times, gate current is approximates an optimally snubbed inductive load. Power not constant. The simplest calculation uses appropriate MOSFETs may be safely operated into an inductive load; values from the capacitance curves in a standard equation for however, snubbing reduces switching losses. voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 1000 C, CAPACITANCE (pF)
VDS = 0 V Ciss
VGS = 0 V
TJ = 25C
800 600 400 200 0 10 5 VGS 0 VDS Crss 5 10 15 20 25 Crss Ciss Coss
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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NTP18N06L, NTB18N06L
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 6 QT Q1 4 Q2 t, TIME (ns) 100 1000 VDS = 30 V ID = 15 A VGS = 5 V tr tf 10 ID = 15 A TJ = 25C 0 0 2 4 6 QG, TOTAL GATE CHARGE (nC) 8 1 1 10 RG, GATE RESISTANCE (W) 100 td(off) td(on)
VGS 2
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
16 IS, SOURCE CURRENT (AMPS) VGS = 0 V 12
8
4
TJ = 150C TJ = 25C
0 0.3
0.6 0.7 0.8 0.9 0.4 0.5 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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NTP18N06L, NTB18N06L
SAFE OPERATING AREA
EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 I D, DRAIN CURRENT (AMPS) VGS = 15 V SINGLE PULSE TC = 25C 10 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100 dc 10 ms 100 ms 70 ID = 11 A 60 50 40 30 20 10 0 25 150 50 75 100 125 175 TJ, STARTING JUNCTION TEMPERATURE (C)
1
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
r(t), TRANSIENT THERMAL RESISTANCE
1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.000001 0.00001 0.0001 0.001 t, TIME (s) 0.01 0.1 1 10
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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NTP18N06L, NTB18N06L INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.42 10.66 0.04 1.016 0.12 3.05 0.63 17.02
0.24 6.096
inches mm
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NTP18N06L, NTB18N06L
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 15 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.
Figure 15. Typical Stencil for DPAK and D2PAK Packages
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.
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CCC C CCC C CC CCCCC CCC C CC CCCCC CCCCC CCC
CC CC CC CC CC CC
SOLDER PASTE OPENINGS
STENCIL
NTP18N06L, NTB18N06L
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joint.
STEP 1 PREHEAT ZONE 1 "RAMP" 200C
STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
STEP 4 HEATING ZONES 3 & 6 "SOAK"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
160C
STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT
150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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NTP18N06L, NTB18N06L
Ordering Information
Device NTP18N06L NTB18N06L NTB18N06LT4 NTB18N06LT4G Package TO-220AB D2PAK D2PAK Pb FREE D2PAK Shipping 50 Units/Rail 50 Units/Rail 800/Tape & Reel 800/Tape & Reel
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NTP18N06L, NTB18N06L
PACKAGE DIMENSIONS
TO-220 CASE 221A-09 ISSUE AA
-T- B
4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04
F T S
C
Q
123
A U K
H Z L V G D N R J
STYLE 5: PIN 1. 2. 3. 4.
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NTP18N06L, NTB18N06L
PACKAGE DIMENSIONS
D2PAK CASE 418AA-01 ISSUE O
C E -B-
4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.036 0.045 0.055 0.310 --- 0.100 BSC 0.018 0.025 0.090 0.110 0.280 --- 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.92 1.14 1.40 7.87 --- 2.54 BSC 0.46 0.64 2.29 2.79 7.11 --- 14.60 15.88 1.14 1.40
V W
A
1 2 3
S
-T-
SEATING PLANE
K G D 3 PL 0.13 (0.005) J
W
DIM A B C D E F G J K M S V
M
TB
M
VARIABLE CONFIGURATION ZONE U
STYLE 2: PIN 1. 2. 3. 4.
GATE DRAIN SOURCE DRAIN
M
M
M
F VIEW W-W 1
F VIEW W-W 2
F VIEW W-W 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTP18N06L/D

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